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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14554B 2-Bit by 2-Bit Parallel Binary Multiplier
The MC14554B 2 x 2-bit parallel binary multiplier is constructed with complementary MOS (CMOS) enhancement mode devices. The multiplier can perform the multiplication of two binary numbers and simultaneously add two other binary numbers to the product. The MC14554B has two multiplicand inputs (X0 and X1), two multiplier inputs (Y0 and Y1), five cascading or adding inputs (K0, K1, M0, M1, and M2), and five sum and carry outputs (S0, S1, S2, C1 [S3], and C0). The basic multiplier can be expanded into a straightforward m-bit by n-bit parallel multiplier without additional logic elements. Application areas include arithmetic processing (multiplying/adding, obtaining square roots, polynomial evaluation, obtaining reciprocals, and dividing), Fast Fourier Transform processing, digital filtering, communications (convolution and correlation), and process and machine controls. * * * * * * * * Diode Protection on All Inputs All Outputs Buffered Straight-forward m-Bit By n-Bit Expansion No Additional Logic Elements Needed for Expansion Multiplies and Adds Simultaneously Positive Logic Design Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range
L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage
Value
Unit V V
- 0.5 to + 18.0 10 500 - 65 to + 150
Vin, Vout Iin, Iout PD Tstg
Input or Output Voltage (DC or Transient)
- 0.5 to VDD + 0.5
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
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Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW
v
v
EQUATIONS
S = (X x Y) + K + M Where: x Means Arithmetic Times. + Means Arithmetic Plus. S = S3 S2 S1 S0, X = X1X0, Y = Y1Y0, K = K1 K0, M = M1 M0 (Binary Numbers). Example: Given: X = 2(1), Y = 3(11) K = 1(01), M = 2(10) Then: S = (2 x 3) + 1 + 2 = 9 S = (10 x 11) + 01 + 10 = 1001
_C
TL Lead Temperature (8-Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
PIN ASSIGNMENT
Y1 M0 M1 C0 M2 C1 (S3) S2 VSS
REV 3 1/94
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VDD Y0 X0 X1 K0 S0 K1 S1
NOTE: C0 connected to M2 for this size multiplier. See general expansion diagram for other size multipliers.
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14554B 1
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (1.0 A/kHz) f + IDD IT = (2.0 A/kHz) f + IDD IT = (3.0 A/kHz) f + IDD Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.0035.
MC14554B 2
MOTOROLA CMOS LOGIC DATA
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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Symbol tTLH, tTHL VDD 5.0 10 15 Min Typ # 100 50 40 Max 200 100 80 Unit ns -- -- Propagation Delay Time K0 to C0 tPLH, tPHL = (1.7 ns/pF) CL + 185 ns tPLH, tPHL = (0.66 ns/pF) CL + 82 ns tPLH, tPHL = (0.5 ns/pF) CL + 60 ns M0 to S2 tPLH, tPHL = (1.7 ns/pF) CL + 595 ns tPLH, tPHL = (0.66 ns/pF) CL + 247 ns tPLH, tPHL = (0.5 ns/pF) CL + 185 ns tPLH, tPHL 5.0 10 15 5.0 10 15 -- -- -- -- -- -- 270 115 85 680 280 210 675 290 215 1700 750 570 ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 20 ns 20 ns VDD 50% tPHL 50% VOL tTLH VOH VOL All outputs connected to respective CL loads. f = system clock frequency tTHL VSS VOH 90% 20 ns 20 ns VDD VSS OUTPUT C0 OR S2 INPUT K0 OR M0 10% tPLH 90% 10% ALL INPUTS (50% DUTY CYCLE) 90% 50% 10% 1 2f ANY OUTPUT (50% DUTY CYCLE) For K0 to C0: Inputs X0, X1, Y0, Y1, K1, and M2 low, and inputs M0 and M1 high. For M0 to S2: Inputs X1, Y1, and K0 low, and inputs X0, Y0, K1, M1, and M2 high.
Figure 1. Dynamic Power Dissipation Waveforms
Figure 2. Dynamic Signal Waveforms
LOGIC DIAGRAM
M1 3 M 4 Y X K MULTIPLIER CELL C S Y1 1 M0 2 M Y X K 12 MULTIPLIER CELL C S Y0 15 14 X0 K0
C0
MULTIPLIER CELL
S L C
M2
5 M MULTIPLIER CELL C S Y X K M Y X 10 K K1 11 S0 13
MULTIPLIER CELL C S 9 S1
X1
M Y X K
6 C1(S3)
7 S2
MOTOROLA CMOS LOGIC DATA
MC14554B 3
EXPANSION DIAGRAM
m-Bit by n-Bit Parallel Binary Multiplier (Top View) Y AND M
Y(n-1) M(n-2) M(n-1)
Y(n-2) X0 X1
Y3 M2 M3
Y2 X0 X1
Y1 M0 M1
VDD Y0 X0 X1 K0 M2 C1 S0 K1 S2 VSS S1 Y1 M0 M1 C0
Y0 X0 X1 K0 K1
Y(n-1) Y(n-2) X2 X3
Y3 Y2 X2 X3
Y1 Y0 X2 X3 K2 K3 X AND K
Y(n-1) Y(n-2) X(m-2) X(m-1)
Y3 Y2 X(m-2) X(m-1)
Y1 Y0 X(m-2) X(m-1) K(m-2) K(m-1)
S(m + n-1)
S(m + n-2)
S(m + n-3)
S(m+2)
S(m+1)
S(m)
S(m-1)
S3 S1 S(m-2) S2 S0
S = (X x Y) + K + M Where: x means Arithmetic Times. S = (X x Y) + K + M Where: + means Arithmetic Plus. S = S(m + n-1) S(m + n-2) ... S2 S1 S0 X = X(m-1) X (m-2) ... X2 X1 X0, Y = Y(n-1) Y(n-2) ... Y2 Y1 Y0 K = K(m-1) K(m-2) ... K2 K1 K0 and M = M(n-1) M(n-2) ... M2 M1 M0 (Binary Numbers). Number of output binary digits = m + n Number of packages = mxn/4 (For m or n of both odd select next highest even number.)
MC14554B 4
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
MC14554B 5
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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MC14554B 6
*MC14554B/D*
MOTOROLA CMOS LOGIC DATA MC14554B/D

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